The talk presents interesting topics in high-level synthesis and heterogeneous computing. The first topic discusses the pipeline synthesis approach to automatic generation of bandwidth-aware and resource-constrained pipelines for the floating-point arithmetic expression in register transfer language. The second topic describes the application of the pipeline synthesis and the FPGA-based kernel acceleration on a heterogeneous computing platform, the Convey HC1. Improving the memory performance for the memory-bound kernels is important. The last topic presents the research in custom memory interface synthesis of FPGA accelerators.