A Field Programmable Gate Array (FPGA) device can be configured to implement a user-specified application. Power consumption is a concern in many FPGA systems, such as battery-powered systems or systems that harness FPGAs to accelerate computation. This talk will focus on novel FPGA architectures and CAD algorithms that enable reducing FPGA’s power by dynamic Power Gating (PG). PG enables powering down components in a device to reduce its static power consumption. Previous PG techniques for FPGAs enable powering down unused components at configuration time only. However, the benefit of this is limited by the number of unused components in a device. On the other hand, the proposed architecture enables dynamically powering down the modules in an application at run-time, based on their behavior, without the need to reconfigure the device. This can lead to significant energy savings for applications with modules that experience long idle periods.