Abstract: Data  movement in computer systems is becoming increasingly energy expensive and is creating bottlenecks that prevent systems from achieving their maximum computational capacity. In this seminar we present a heterogeneous architecture that uses the Recode-Engine, an innovative data recoding accelerator, in conjunction with a CPU core for Sparse Matrix-Vector Multiplication, a kernel found in many scientific applications. Using CPU-RecodeEngine for SpMV on sparse matrices from the TAMU sparse matrix library, we obtained geometric mean performance gain of 2.4x. The Recode-Engine is part of the P38 project, a cross-agency effort  that explores new architectural features that improve memory system performance.